1. Field of the Invention
This invention relates to a MOS (Metal Oxide Semiconductor) type field effect transistor formed on a semiconductor layer on an insulator substrate, referred to hereinafter as SOI-MOSFET, and more particularly, to an improvement in the source to drain voltage withstand characteristics of SOI-MOSFET devices.
2. Description of the Related Art
Referring to FIG. 8, there is shown a conventional SOI-MOSFET is a cross section. An insulator layer 2 is formed on a silicon substrate 1 and a silicon layer 3 is formed on the insulator layer. A channel region 6 containing p-type impurities at a low concentration of, for example, 10.sup.16 -10.sup.17 atoms/cm.sup.3, is formed within the silicon layer 3, while a source region 7 and a drain region 8, both having high n-type impurity concentration of, for example, 10.sup.19 -10.sup.21 atoms/cm.sup.3, are formed in contact with one side and the other side of the channel region 6, respectively.
On the channel region 6, a dielectric thin film 4 acting as a gate is formed, and a gate electrode 5 is formed on the dielectric thin film 4. The silicon layer 3 and the gate electrode 5 are covered by an interlayer insulating film 11. Contact holes 12a, 12b are formed in the interlayer insulating film 11, and electrical conductors 13a, 13b are formed in register with these contact holes.
In the above described SOI-MOSFET, when a positive voltage is applied to the gate electrode 5, n-conductivity type carriers or electrons are attracted towards an upper portion of the p-type channel region 6. The conductivity type of this upper portion is inverted to n-type which is the same as the conductivity type of the source region 7 and the drain region 8. Thus the current is allowed to flow between the source region 7 and the drain region 8. Inasmuch as the n-type carriers attracted towards the upper portion of the channel region 6 are changed in concentration with the gate voltage, the amount of the current flowing through the channel region 6 may be controlled by the gate voltage. The above is the operating principle of both the conventional MOSFET and SOI-MOSFET.
As schematically illustrated in FIG. 9, when the drain voltage is increased in a SOI-MOSFET formed on a silicon layer 3 having a larger thickness of about 5000 .ANG., a depletion layer (shown by a broken line) in the vicinity of the drain 8 is extended toward the source 7 particularly in a deeper region where it is difficult to control the potential by the gate electrode. When the depletion layer reaches and is combined with another depletion layer (also shown by another broken line) formed in the vicinity of the source 7, there occurs a phenomenon known as the punch-through phenomenon, in which the electrical barrier between the source 7 and the channel is lowered and the potential at the deeper region that cannot be controlled by the gate electrode is increased so that the channel current is increased suddenly. The punch-through of carriers is shown by an arrow in FIG. 9 and this may lower the source to drain withstand voltage characteristics.
Also, when a high voltage is applied across the source and the drain, the carriers are accelerated to a higher velocity within the channel region 6. With these carriers accelerated within the channel region 6, electron and positive hole pairs are produced in the vicinity of the drain region 8 due to ionization by collision which can occur at voltages which may be less than voltages at which the punch-through effect occurs. The electrons thus produced flow into a n.sup.+ type drain region 8. As schematically illustrated in FIG. 10, in case of a conventional MOSFET formed on a bulky silicon substrate 3a, the produced positive holes can be removed through a substrate electrode to the ground. In a SOI-MOSFET, however, since the positive holes are stored in the channel region 6 formed on the insulator 2 and thus raise the potential of the channel region in normal operation, when excess holes are generated by ionization, the potential of the channel region and the channel current are further increased to produce undesirable kink effect on a curve representing the relation between the drain voltage and the drain current. FIG. 11 shows examples of such kinks on curves representing the relation between the drain voltage V.sub.D and the drain current I.sub.D, where arrows directing downward indicate the kink effect and arrows directing upward indicate the punch-through phenomenon. This kink effect is discussed for in, for example, IEEE Electron Device Letter. Vol. 9, No. 2, pp. 97-99, 1988.
On the other hand, as also discussed in this article, the thin film SOI-MOSFET having an extremely thin silicon layer 3 with, for example, 500-1500 .ANG. has superior properties as compared with the usual SOI-MOSFET having a thicker silicon layer 3. For example, its thin channel region 6 is turned as a whole into a depletion layer, upon application of a voltage to the gate electrode 5, while the potential is controlled by the gate electrode, so that the aforementioned punch-through phenomenon in the deeper layer of the channel region and the kink effect are eliminated. Also the short channel effect, in which the gate threshold voltage is unusually lowered in case of a shorter gate length, is also reduced, since the depletion layer controlled by the gate will extend for the entire depth of the thin channel region.
However, when the channel region 6 as a whole is turned into a depletion layer, the potential within the channel region 6 becomes higher than in the case of the conventional MOSFET. Thus the electrical barrier between the source region 7 and the channel region 6 and, hence, the threshold of the transistor is lowered. Moreover, when the positive holes produced by the aforementioned ionization upon collision are stored temporarily in the channel region 6, the potential within the channel region 6 is increased further so that electrons are introduced abruptly from the source region 7 into the channel region 6. That is, the breakdown voltage characteristics between the source and the drain is inconveniently lowered even in the thin film SOI-MOSFET.